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AS1117 64 led driver for mobile applications with error detection www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 1 - 23 datasheet 1 general description the AS1117 is a compact led driver for 64 single leds or 8 digits of 7-segments. the devices can be pro- grammed via an i2c compatib le 2-wire interface. every segment can be individually addressed and updated separately. only one external resistor (r set ) is required to set the current. led brightness can be controlled by analog or digital means. the devices include an in tegrated bcd code-b/hex decoder, multiplex scan circuitry, segment and display drivers, and a 64-bit memory. internal memory stores the shift register settings, e liminating the need for contin- uous device reprogramming. additionally the AS1117 offers a detailed error diagnostic mode for easy and fast production testing in critical applications. the AS1117 features a low shutdown cur- rent of typically 200na, and an operational current of typically 350a. the number of digits can be pro- grammed, the devices can be reset by software, and an external clock is also supported. the device is available in a tqfn(4x4)-24 package. figure 1. AS1117 - typical application diagram 2 key features 3.4mhz i2c-compatible interface individual led segment control readback for 8 keys plus interrupt open and shorted led error detection - global or individual error detection hexadecimal- or bcd-code for 7-segment displays 200na low-power shutdown current (typ; data retained) digital and analog brightness control display blanked on power-up drive common-cathode led displays supply voltage range: 2.7v to 5.5v software and hardware reset up to 4 devices cascadable optional external clock package: tqfn(4x4)-24 3 applications the AS1117 is ideal for seven-segment or dot matrix user interface displays of mobile applications, set-top boxes, vcrs, dvd-players, washing machines, micro wave ovens, refrigerators a nd other white good or per- sonal electronic applications. table 1. available products devices reset input interfaces as1115 no i2c as1116 no spi AS1117 yes i2c as1118 yes spi AS1117 dig0 to dig7 sega-dp key0-7 8 sda scl irq v dd i set sda irq gnd scl 2.7v to 5.5v 9.53k p 8 key resetn vdd ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 2 - 23 AS1117 datasheet - pinout 4 pinout pin assignments figure 2. pin assignments (top view) pin descriptions table 2. pin descriptions pin name pin number description sda 22 serial-data i/o . open drain digital i/o i2c data pin. dig0:dig7 1, 2, 4, 5, 6, 7, 23, 24 digit drive lines . eight digit drive lines that sink current from the display common cathode. keyscan detection opt ional, but must be polled by the prozessor. gnd 3 ground . key 8 keyscan input. keyscan lines for key readback. can be used for self-adressing. resetn 9 reset input. pull this pin to low to resest a ll registers (set to default values) and to put the device into shutdown. connect this pin via a pull-up resistor to v dd for normal operation. i set 10 set segment current . connect to v dd or a reference voltage through r set to set the peak segment current (see selecting rset resistor value and using external drivers on page 19 ). scl 11 serial-clock input . 3.4mhz maximum rate. irq 21 interupt request output . open drain pin. sega:segg, segdp 12-15, 17-20 seven segment and decimal point drive lines . 8 seven-segment drives and decimal point drive that source current to the display. v dd 16 positive supply voltage . connect to +2.7v to +5.5v supply. bypass this pin to gnd with a 0.1f capacitor to avoid power supply ripple. exposed pad exposed pad. this pin also functions as a heat sink. solder it to a large pad or to the circuit-board ground plane to maximize power dissipation. seg e key 8 18 segb 14 dig2 1 gnd 3 AS1117 dig5 5 i set 10 sega 12 vdd 16 segc 17 segg 15 segf 13 dig3 2 dig4 4 dig6 6 scl 11 resetn 9 dig7 7 dig0 23 irq 21 segdp 19 segd 20 sda 22 dig1 24 exposed pad ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 3 - 23 AS1117 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other cond itions beyond those indicated in section 6 electrical characteristics on page 4 is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units notes input voltage range v dd to gnd -0.3 7 v all other pins to gnd -0.3 7 or v dd + 0.3 v current dig0:dig7 sink current 500 ma sega:segg, segdp 100 ma humidity 5 85 % non-condensing esd digital outputs 1 kv norm: mil 833 e method 3015 all other pins latch-up immunity 100 ma eia/jesd78 thermal resistance ja 30.5 oc/w on pcb ambient temperature -40 +85 oc storage temperature -55 150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020d ?moisture/ reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 4 - 23 AS1117 datasheet - electrical characteristics 6 electrical characteristics v dd = 2.7v to 5.5v, r set = 9.53k , t amb = -40c to +85c, typ. values @ t amb = +25oc and v dd = 5.0v (unless oth- erwise specified). table 4. electrical characteristics symbol parameter conditions min typ max unit v dd operating supply voltage 2.7 5.5 v i ddsd shutdown supply current all digital inputs at v dd or gnd, t amb = +25oc 0.2 2 a i dd operating supply current r set = open circuit. 0.35 0.6 ma all segments and decimal point on; i seg = -40ma. 335 f osc display scan rate 8 digits scanned 0.48 0.96 khz i digit digit drive sink current v out = 0.65v 320 ma i seg segment drive source current v dd = 5.0v, v out = (v dd -1v) -35 -41 -47 ma i seg segment drive current matching 3 % i seg segment drive source current average current 47 ma table 5. logic inputs/outputs characteristics symbol parameter conditions min typ max unit i ih , i il input current sda, scl v in = 0v or v dd -1 1 a v ih logic high input voltage sda, scl, resetn 1.26 v v il logic low input voltage sda, scl, resetn 0.54 v v ol(sda) sda output low voltage i sink = 3ma 0.4 v v keyopen keyscan open input voltage 0.8xv dd v v keyshort keyscan short input voltage 0.7x v dd v v ol(irq) interrupt output low voltage i sink = 3ma 0.4 v v i hysteresis voltage din, clk, ld/cs 1 v capacitive load for each bus line 400 pf open detection level threshold 0.7x v dd 0.75x v dd 0.8x v dd v short detection level threshold 0.05x v dd 0.1x v dd 0.15x v dd v ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 5 - 23 AS1117 datasheet - electrical characteristics notes: 1. the min / max values of the timing characteristics are guaranteed by design. 2. all limits are guaranteed. the pa rameters with min and max values are gua ranteed with production tests or sqc (statistical qualit y control) methods. figure 3. timing diagram table 6. timing characteristics symbol parameter conditions min typ max unit f scl scl frequency 0.1 3.4 mhz t buf bus free time between stop and start conditions 1.3 s t holdstart hold time for repeated start condition 160 ns t low scl low period 50 75 ns t high scl high period 50 75 ns t setupstart setup time for repeated start condition 100 ns t setupdata data setup time 10 ns t holddata data hold time 70 ns t rise(scl) scl rise time 10 40 ns t rise(scl1) scl rise time after repeated start condition and after an ack bit 10 80 ns t fall(scl) scl fall time 10 40 ns t rise(sda) sda rise time 20 80 ns t fall(sda) sda fall time 20 80 ns t setupstop stop condition setup time 160 ns t spikesup pulse width of spike suppressed 50 ns key readback debounce time 20 ms repeated start sdi scl start stop t buf t low t holdstart t holddata t r t high t f t setupdata t holdstart t spikesup t setupstop t setupstart ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 6 - 23 AS1117 datasheet - typical operating characteristics 7 typical operating characteristics r set = 9.53k , v rset = v dd ; figure 4. display scan rate vs. supply voltage; figure 5. display scan rate vs. temperature; 680 700 720 740 760 780 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 vd d (v) fosc (hz) . tamb=-40c tamb =+2 5c tamb =+8 5c 680 700 720 740 760 780 800 -40 -15 10 35 60 85 tam b (c) fosc (hz) . vdd=2.7v vdd=4v vdd=5v v d d =5.5v figure 6. segment current vs. temperat ure; figure 7. segment current vs. r set ; 0 10 20 30 40 50 60 -40 -15 10 35 60 85 tam b (c) iseg (ma) . v seg = 1.7v ; v d d = 2 .7v v seg = 1.7v ; v d d = 5v v seg = 3 v ; v d d = 5v v seg = 4 v ; v d d = 5v 0 10 20 30 40 50 0 102030405060708090 rset (kohm) iseg (ma) . vseg = 4v; vdd = 5v vseg = 3v; vdd = 5v vseg = 2v; vdd = 5v v seg = 1.7v ; v d d = 2 .7v figure 8. segment current vs. supply voltage; figure 9. segment current vs. v dd ; v rset = 2.8v 0 10 20 30 40 50 60 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 vd d (v) iseg (ma) . v seg = 1.7v vseg = 3v vseg = 4v 0 5 10 15 20 25 30 35 40 45 50 2.7 3 3.3 3.6 3.9 4.2 vd d (v) iseg (ma) . v seg = 1.7v vseg = 2v vseg = 2.3v vseg = 3.1v ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 7 - 23 AS1117 datasheet - typical operating characteristics figure 10. v digit vs. i digit figure 11. input high level vs. supply voltage 0 0.1 0.2 0.3 0.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 idig (a) vdig (v) . vdd = 2.7v vdd = 3.3v vdd = 4v vdd = 5v v d d = 5.5v 0 0.5 1 1.5 2 2.5 3 3.5 2.73.13.53.94.34.75.15.5 vd d (v) vih (v) . figure 12. i seg vs. v seg ; v dd = 5v figure 13. i seg vs. v seg ; v dd = 4v 0 5 10 15 20 25 30 35 40 45 50 2 2.5 3 3.5 4 4.5 5 vs e g (v) iseg (ma) . rext = 10k rext = 13k rext = 18k rext = 30k rext = 56k 0 5 10 15 20 25 30 35 40 45 50 11.522.533.54 vs e g (v) iseg (ma) . rext = 8k2 rext = 10k rext = 13k rext = 18k rext = 30k figure 14. i seg vs. v seg ; v dd = 3.3v figure 15. i seg vs. v seg ; v dd = 2.7v 0 5 10 15 20 25 30 35 40 45 50 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 vs e g (v) iseg (ma) . rext = 6k8 rext = 8k2 rext = 10k rext = 13k rext = 18k 0 5 10 15 20 25 30 35 40 45 50 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vs e g (v) iseg (ma) . rext = 4k 7 rext = 5k6 rext = 6k8 rext = 10k rext = 13k ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 8 - 23 AS1117 datasheet - detailed description 8 detailed description block diagram figure 16. AS1117 - block diagram figure 17. esd structure AS1117 registers digital control logic oszillator open/short detection i2c interface + ? + ? scan - registers control - registers data - registers (pwm, debounce,....) r set 10 iset 12-15, 17-20 sega-g, segdp 1,2,4,5,6,7,23,24 dig0 to dig7 3 gnd vdd 8 8 vdd vdd vdd 22 sda 11 scl 21 irq 16 vdd 8 key 100nf 9 resetn vdd vdd valid for the pins: - irq - scl - sda - iset - sega-g, segdp - key - resetn vdd valid for the pins: - dig0 to dig7 ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 9 - 23 AS1117 datasheet - detailed description i2c interface the AS1117 supports the i2c serial bus and data transmis sion protocol in high-speed mode at 3.4mhz. the AS1117 operates as a slave on the i2c bus. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. connections to the bus are made via the open-drain i/o pins scl and sda. figure 18. i2c interface initialisation figure 19. bus protocol the bus protocol (as shown in figure 19 ) is defined as: - data transfer may be initiated only when the bus is not busy. - during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. the bus conditions are defined as: - bus not busy . data and clock lines remain high. - start data transfer . a change in the state of the data line, from high to low, while the clock is high, defines a start condition. - stop data transfe r. a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. - data valid . the state of the data line represents valid data, when, after a start condition, the data line is stable for the duration of the high period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth-bit. within the i2c bus specifications a high-speed mode (3.4mhz clock rate) is defined. - acknowledge : each receiving device, when addressed, is obliged to generate an acknowledge after the recep- tion of each byte. the master device must generate an extr a clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an 19 81 9 8 0 0 0 00 a1 a0 r/w d15 d14 d13 d12 d11 d10 d9 d8 default values at power up: a1 = a0 = 0 sdi scl slave address r/w direction bit start 1 2 6 7 8 9 1 23-8 8 9 ack msb repeat if more bytes transferred stop or repeated start ack from receiver ack from receiver ack ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 10 - 23 AS1117 datasheet - detailed description acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. - figure 19 on page 9 details how data transfer is accomplished on the i2c bus. depending upon the state of the r/ w bit, two types of data transfer are possible: - master transmitter to slave receiver . the first byte transmitted by the master is the slave address, followed by a number of data bytes. the slave returns an acknowledge bit after the slave address and each received byte. - slave transmitter to master receiver . the first byte, the slave address, is transmitted by the master. the slave then returns an acknowledge bit. next, a number of data bytes are transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not-acknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the AS1117 can operate in the following slave modes: - slave receiver mode . serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is per formed by hardware after reception of the slave address and direction bit. - slave transmitter mode . the first byte (the slave address) is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the AS1117 while the serial clock is input on scl. start and stop conditions are recog- nized as the beginning and end of a serial transfer. i2c device self addressing if this feature is used, 2 of the 8 key readback nodes can be left open or shorted for self-addressing. this is done with key together with segg and segf. this two nodes cannot be used for key-readback in this case. after startup all devices have the predefined adress 0000000. a single command for self-addressing will update all connected AS1117. this command has to be done after startup or everytime the AS1117 gets disconnected from the supply. the i2c address definition must be done with fixed connection, since i2c detection is excluded from debounce time of key reg- isters. i2c device address byte the address byte (see figure 20) is the first byte received following the start condition from the master device. figure 20. i2c device address byte - the default slave address is factory-set to 0000000. - the two lsb bits of the address byte are the device select bits, a0 to a1, which can be set by the self-adress command after startup. a maximum of four devices with the same pre-set code can therefore be connected on the same bus at one time. - the last bit of the address byte (r/w ) define the operation to be performed. when set to a 1 a read operation is selected; when set to a 0 a write operation is selected. following the start condition, the AS1117 monitors the i2c bus, checking the device type identifier being transmitted. upon receiving the address code, and the r/w bit, the slave device outputs an acknowledge signal on the sda line. 0 0 0 0 0 0 0 r/w msb654321lsb 0 0 0 0 0 a1 a0 r/w msb654321lsb predefined address: updated address: ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 11 - 23 AS1117 datasheet - detailed description command byte the AS1117 operation, (see table 7) is determined by a command byte ( see figure 21 on page 11 ). figure 21. command byte figure 22. command and single data byte received figure 23. setting the pointer to a address register to select a data register for a read operation figure 24. reading nbytes from AS1117 d15 d14 d13 d12 d11 d10 d09 d08 msb654321lsb from master to slave from slave to master aa p a s command byte data byte slave address d14 d13 d12 d11 d10 d9 d8 d15 d6 d5 d4 d3 d2 d1 d0 d7 acknowledge from AS1117 0 0 0 acknowledge from AS1117 acknowledge from AS1117 r/w 0 AS1117 registers autoincrement memory word address 1 byte from master to slave from slave to master ap a s command byte slave address d14 d13 d12 d11 d10 d9 d8 d15 0 0 acknowledge from AS1117 acknowledge from AS1117 r/w 0 AS1117 registers from master to slave from slave to master a/ a p a s first data byte second data byte slave address d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 not acknowledge from master 0 1 0 acknowledge from master acknowledge from AS1117 r/w 1 AS1117 registers autoincrement memory word address n bytes autoincrement to next address stop reading ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 12 - 23 AS1117 datasheet - detailed description initial power-up on initial power-up, the AS1117 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. at this time, all registers should be programmed for normal operation. note: the default settings enable only scanning of one digit; the internal decoder is disabled and the intensity control register ( see page 17 ) is set to the minimum values. shutdown mode the AS1117 devices feature a shutdown mode, where they consume only 200na (typ) current. shutdown mode is entered via a write to the shutdown register (see ta b l e 8 ) or via pulling the pin resten to logic low. when pin resetn is set to logic low an according write to the shut down register is done internally. during shutdown mode the digit-registers maintain their data. note: when pin resetn is pulled to logic high again, a write to the shutdown register in necessary to leave the shutdown mode. shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display (repeatedly entering and leaving shutdown mode). for minimum supply current in shutdown mode, logic input should be at gnd or v dd (cmos logic level). when entering or leaving shutdown mode, the feature register is reset to its default values (all 0s) when shutdown register bit d7 (page 13) = 0. note: when shutdown register bit d7 = 1, the feature register is left unchanged when entering or leaving shut- down mode. if the AS1117 is used with an external clock, shutdown register bit d7 should be set to 1 when writing to the shutdown register. digit- and cont rol-registers the AS1117 devices contain 8 digit-registers,11 control-registers and 10 diagnostic-registers, which are listed in table 7 . all registers are selected using a 8-bit address word, and communication is done via the i2c interface. digit registers ? these registers are realized with an on-c hip 64-bit memory. each digit can be controlled directly without rewriting the whole register contents. control registers ? these registers consist of decode mode, display intensity, number of scanned digits, shut- down, display test and features selection registers. table 7. register address map type register address page d15:d13 d12 d11 d10 d9 d8 d7:d0 digit register digit 0 000 0 0 0 0 1 (see table 10 on page 14 , table 11 on page 14 and table 12 on page 15 ) n/a digit 1 000 0 0 0 1 0 n/a digit 2 000 0 0 0 1 1 n/a digit 3 000 0 0 1 0 0 n/a digit 4 000 0 0 1 0 1 n/a digit 5 000 0 0 1 1 0 n/a digit 6 000 0 0 1 1 1 n/a digit 7 000 0 1 0 0 0 n/a ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 13 - 23 AS1117 datasheet - detailed description the shutdown register controls AS1117 shutdown mode. decode enable register (0x09) the decode enable register sets the decode mode. bcd/hex decoding (either bcd code ? characters 0:9, e, h, l, p, and -, or hex code ? characters 0:9 and a:f) is selected by bit d2 (page 18) of the feature register. the decode enable register is used to select the decode mode or no-decode for each digit. each bit in the decode enable regis- ter corresponds to its respective display digit (i.e., bit d0 corresponds to digit 0, bit d1 corresponds to digit 1 and so on). table 10 on page 14 lists some examples of the possible settings for the decode enable register bits. note: a logic high enables decoding and a logic low bypasses the decoder altogether. when decode mode is used, the decoder looks only at the lower-nibble (bits d3:d0) of the data in the digit-registers, disregarding bits d6:d4. bit d7 sets the decimal point (seg dp) independent of the decoder and is positive logic (bit d7 = 1 turns the decimal point on). table 10 on page 14 lists the code-b font; table 11 on page 14 lists the hex font. control register decode-mode 000 0 1 0 0 1 ( see table 9 on page 14 ) 13 global intensity 000 0 1 0 1 0 ( see table 18 on page 17 ) 17 scan limit 000 0 1 0 1 1 ( see table 20 on page 17 ) 17 shutdown 000 0 1 1 0 0 ( see table 8 on page 13 ) 12 self-adressing 001 0 1 1 0 1 n/a feature 000 0 1 1 1 0 ( see table 21 on page 18 ) 18 display test mode 000 0 1 1 1 1 ( see table 15 on page 16 ) 14 dig0:dig1 intensity 000 1 0 0 0 0 ( see table 19 on page 17 ) dig2:dig3 intensity 000 1 0 0 0 1 ( see table 19 on page 17 ) dig4:dig5 intensity 000 1 0 0 1 0 ( see table 19 on page 17 ) dig6:dig7 intensity 000 1 0 0 1 1 ( see table 19 on page 17 ) keyscan/diagnostic register diagnostic digit 0 000 1 0 1 0 0 n/a diagnostic digit 1 000 1 0 1 0 1 n/a diagnostic digit 2 000 1 0 1 1 0 n/a diagnostic digit 3 000 1 1 0 1 1 n/a diagnostic digit 4 000 1 1 0 0 0 n/a diagnostic digit 5 000 1 1 0 0 1 n/a diagnostic digit 6 000 1 1 0 1 0 n/a diagnostic digit 7 000 1 1 0 1 1 n/a key 000 1 1 1 0 0 table 8. shutdown register format (address (hex) = 0x0c)) mode hex code register data d7 d6 d5 d4 d3 d2 d1 d0 shutdown mode, reset feature register to default settings 0x00 0xxxxxx0 shutdown mode, feature register unchanged 0x80 1xxxxxx0 normal operation, reset feature register to default settings 0x01 0xxxxxx1 normal operation, feature register unchanged 0x81 1 xxxxxx1 table 7. register address map type register address page d15:d13 d12 d11 d10 d9 d8 d7:d0 ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 14 - 23 AS1117 datasheet - detailed description when no-decode mode is selected, data bits d7:d0 of the digit-registers correspond to the segment lines of the AS1117. table 12 on page 15 shows the 1:1 pairing of each data bit to the appropriate segment line. figure 25. standard 7-segment led in tensity control and inter-digit blanking table 9. decode enable register format examples decode mode hex code register data d7 d6 d5 d4 d3 d2 d1 d0 no decode for digits 7:0 0x00 0000000 0 code-b/hex decode for digit 0. no decode for digits 7:1 0x01 00000001 code-b/hex decode for digit 0:2. no decode for digits 7:3 0x07 00000111 code-b/hex decode for digits 0:5. no decode for digits 7:6 0x3f 00111111 code-b/hex decode for digits 0,2,5. no decode for digits 1, 3, 4, 6, 7 0x25 00100101 table 10. code-b font char- acter register data char- acter register data char- acter register data d7 d6:d4 d3 d2 d1 d0 d7 d6: d4 d3 d2 d1 d0 d7 d6:d4 d3 d2 d1 d0 x 0000 x 0110 x 1100 x 0001 x 0111 x 1101 x 0010 x 1000 x 1110 x 0011 x 1001 x 1111 x 0100 x 1010 1 * xxxxx x 0101 x 1011 * the decimal point can be enabled with every character by setting bit d7 = 1. table 11. hex font char- acter register data char- acter register data char- acter register data d7 d6:d4 d3 d2 d1 d0 d7 d6: d4 d3 d2 d1 d0 d7 d6:d4 d3 d2 d1 d0 x 0000 x 0110 x 1100 x 0001 x 0111 x 1101 x 0010 x 1000 x 1110 a b g f e d c dp ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 15 - 23 AS1117 datasheet - detailed description i2c self addressing if this feature is used, 2 of the 8 key readback nodes can be left open or shorted for self-addressing. this is done with key together with segg and segf. this two nodes cannot be used for key-readback in this case. after startup all devices have the predefined adress 0000000. a single co mmand for selfaddressing will upd ate all connected AS1117. this command has to be done after startup or everytime the AS1117 gets disconnected from the supply. the i2c address definition must be done with fixed connection, since i2c detection is excluded from debounce time of key reg- isters. note: a short writes a logical ?0? whereas an open writes a logical ?1? as address bit. keyscan register these two registers contain the result of the keyscan input of the 8 keys. to ensure proper results the data in these registers are updated only if the logic data scanned is stable for 20ms (debounce time). a change of the data stored within these two registers is indicated by a logic low on the irq pin. the irq is high-impedance if a read operation on the key scan registers is started. note: if i2c self addressing is used segment g&f of key is used for the two lsb of the i2c address. in this case these two nodes cannot be used as a key. additionally the debounce time is disabled for these two bits. the data within the keyscan register is updated conti nuously during every cycle (1/10 of refresh rate). there- fore, to get a valid readback of keys it is recommended to read out the keyscan registers immediately after the irq is triggered. a short writes a logical ?0? whereas an open writes a logical ?1? as keyscan register bit. x 0011 x 1001 x 1111 x 0100 x 1010 1 * xxxxx x 0101 x 1011 * the decimal point can be enabled with every character by setting bit d7 = 1. table 12. no-decode mode data bits and corresponding segment lines d7 d6 d5 d4 d3 d2 d1 d0 corresponding segment line dp a b c d e f g table 13. self addressing register (address (hex) = 0x2d)) d7 d6 d5 d4 d3 d2 d1 d0 factory-set ic address xxxxxxx0 user-set ic address x x xxxxx1 table 14. led diagnostic register address register hex address segment d7 d6 d5 d4 d3 d2 d1 d0 0x1c key dp a b c d e f g table 11. hex font char- acter register data char- acter register data char- acter register data d7 d6:d4 d3 d2 d1 d0 d7 d6: d4 d3 d2 d1 d0 d7 d6:d4 d3 d2 d1 d0 ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 16 - 23 AS1117 datasheet - detailed description display-test mode the AS1117 can detect open or shorted leds. readout of either open leds or short leds is possible, as well as a or relation of open and short. note: all settings of the digit- and control-registers are maintained. led diagnostic registers these eight registers contain the result of the led open/short test for the individual led of each digit. note: if one or more short occures in the led array, detection of individual led fault could become ambiguous. intensity control register (0x0a) the brightness of the display can be controlled by digital means using the intensity control registers and by analog means using r set (see selecting rset resistor value and using external drivers on page 19 ). the intensity can be controlled globally for all digits, or for each digit individually. the global intensity command will write intensity data to a ll four individual brightness registers, while the individual intesity command will only write to the associated individual intensity register. table 15. testmode register summary d7 d6 d5 d4 d3 d2 d1 d0 x rset_short rset_open led_global led_test led_open led_short disp_test table 16. testmode register bit description (address (hex) = 0x0f)) addr: 0x0f address bit bit name default access d7:d0 d0 disp_test 0 w optical display test. (testmode for external visual test.) 0: normal operation; 1: run display test (all digits are tested independently from scan limit & shutdown register.) d1 led_short 0 w starts a test for shorted leds. (can be set together with d2) 0: normal operation; 1: activate testmode d2 led_open 0 w starts a test for open leds. (can be set together with d1) 0: normal operation; 1: activate testmode d3 led_test 0 r indicates an ongoing open/short led test 0: no ongoing led test; 1: led test in progress d4 led_global 0 r indicates that the last open/short led test has detected an error 0: no error detected; 1: error detected d5 rset_open 0 r checks if external resistor r set is open 0: r set correct; 1: r set is open d6 rset_short 0 r checks if external resistor r set is shorted 0: r set correct; 1: r set is shorted d7 0 - not used table 17. led diagnostic register address register hex address segment register hex address segment digit d7 d6 d5 d4 d3 d2 d1 d0 digit d7 d6 d5 d4 d3 d2 d1 d0 0x14 dig0 dp a b c d e f g 0x18 dig4 dp a b c d e f g 0x15 dig1 0x19 dig5 0x16 dig2 0x1a dig6 0x17 dig3 0x1b dig7 ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 17 - 23 AS1117 datasheet - detailed description display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the intensity control register. the modulator scales the average segment-current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current set by r set . scan-limit register (0x0b) the scan-limit register controls which of the digits are to be displayed. when all 8 digits are to be displayed, the update frequency is typically 700hz. if the number of digi ts displayed is reduced, the update frequency is increased. the frequency can be calculated using 10 x fosc/(n+2), where n is the number of digits. note: to avoid differences in brightness this register should not be used to blank parts of the display (leading zeros). table 18. intensity register format duty cycle hex code register data duty cycle hex code register data msb d2 d1 lsb msb d2 d1 lsb 1/16 (min on) 0xx0 0 0 0 0 9/16 0xx8 1 0 0 0 2/16 0xx1 0 0 0 1 10/16 0xx9 1 0 0 1 3/16 0xx2 0010 11/16 0xxa 1010 4/16 0xx3 0 0 1 1 12/16 0xxb 1 0 1 1 5/16 0xx4 0 1 0 0 13/16 0xxc 1 1 0 0 6/16 0xx5 0 1 0 1 14/16 0xxd 1 1 0 1 7/16 0xx6 0 1 1 0 15/16 0xxe 1 1 1 0 8/16 0xx7 0 1 1 1 15/16 (max on) 0xxf 1 1 1 1 table 19. intensit y register address register hex address register data type d7:d4 d3:d0 0x0a global x global intensity 0x10 digit digit 1 intensity digit 0 intensity 0x11 digit digit 3 intensity digit 2 intensity 0x12 digit digit 5 intensity digit 4 intensity 0x13 digit digit 7 intensity digit 6 intensity table 20. scan-limit register format (address (hex) = 0x0b)) scan limit hex code register data scan limit hex code register data d7:d3 d2 d1 d0 d7:d3 d2 d1 d0 display digit 0 only 0xx0 x 0 0 0 display digits 0:4 0xx4 x 1 0 0 display digits 0:1 0xx1 x 0 0 1 display digits 0:5 0xx5 x 1 0 1 display digits 0:2 0xx2 x 0 1 0 display digits 0:6 0xx6 x 1 1 0 display digits 0:3 0xx3 x 0 1 1 display digits 0:7 0xx7 x 1 1 1 ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 18 - 23 AS1117 datasheet - detailed description feature register (0x0e) the feature register is used for enabling various features including switching the device into external clock mode, applying an external reset, selecting code-b or hex decoding, enabling or disabling blinking, setting the blinking rate, and resetting the blink timing. note: at power-up the feature register is initialized to 0. table 21. feature register summary d7 d6 d5 d4 d3 d2 d1 d0 blink_ start sync blink_ freq_sel blink_en nu decode_sel reg_res clk_en table 22. feature register bit descriptions (address (hex) = 0xxe) addr: 0xxe feature register enables and disables various device features. bit bit name default access bit description d0 clk_en 0r/w external clock active. 0 = internal oscillator is used for system clock. 1 = pin clk of the serial interface operates as system clock input. d1 reg_res 0r/w resets all control registers except the feature register. 0 = reset disabled. normal operation. 1 = all control registers are reset to default state (except the feature register) identically after power-up. note: the digit registers maintain their data. d2 decode_sel 0r/w selects display decoding for the selected digits ( table 9 on page 14 ). 0 = enable code-b decoding (see table 10 on page 14 ). 1 = enable hex decoding (see table 11 on page 14 ). d3 nu not used d4 blink_en 0r/w enables blinking. 0 = disable blinking. 1 = enable blinking. d5 blink_freq_sel 0r/w sets blink with low frequency (with the internal oscillator enabled): 0 = blink period typically is 1 second (0.5s on, 0.5s off). 1 = blink period is 2 seconds (1s on, 1s off). d6 sync 0r/w synchronizes blinking on the rising edge of pin ld/cs. the multiplex and blink timing counter is cleared on the rising edge of pin ld/cs. by setting this bit in multiple devices, the blink timing can be synchronized across all the devices. d7 blink_start 0r/w start blinking with display enabled phase. when bit d4 (blink_en) is set, bit d7 determines how blinking starts. 0 = blinking starts with the display turned off. 1 = blinking starts with the display turned on. ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 19 - 23 AS1117 datasheet - typical application 9 typical application selecting r set resistor value and us ing external drivers brightness of the display segments is controlled via r set . the current that flows into i set defines the current that flows through the leds. segment current is about 200 times the current in i set . typical values for r set for different segment currents, operat- ing voltages, and led voltage drop (v led ) are given in table 23 & table 24 . the maximum current the AS1117 can drive is 47ma. if higher currents are needed, external driver s must be used, in which case it is no longer necessary that the devices drive high currents. note: the display brightness can also be logically controlled (see intensity control register (0x0a) on page 16) . calculating power dissipation the upper limit for power dissipation (pd) for the AS1117 is determined from the following equation: pd = (v dd x 5ma) + (v dd - v led )(duty x i seg x n) (eq 1) where: v dd is the supply voltage. duty is the duty cycle set by intensity register (page 17) . n is the number of segments driven (worst case is 8) v led is the led forward voltage i seg = segment current set by rset dissipation example: i seg = 40ma, n = 8, duty = 15/16, v led = 2.2v at 40ma, v dd = 5v (eq 2) pd = 5v(5ma) + (5v - 2.2v)(15/16 x 40ma x 8) = 0.865w (eq 3) thus, for a tqfn(4x4)-24 package ja = +30.5c/w, the maximum allowed t amb is given by: t j,max = t amb + pd x ja = 150c = t amb + 0.865w x 30.5c/w (eq 4) in this example the maximum ambient temperature must stay below 123.61c. table 23. r set vs. segment current and led forward voltage, v dd = 2.7v & 3.3v & 3.6v i seg (ma) v led v led v led 1.5v 2.0v 1.5v 2.0v 2.5v 1.5v 2.0v 2.5v 3.0v 40 v dd = 2.7v 5k 4.4k v dd = 3.3v 6.7k 6.4k 5.7k v dd = 3.6v 7.5k 7.2k 6.6k 5.5k 30 6.9k 5.9k 9.1k 8.8k 8.1k 10.18k 9.8k 9.2k 7.5k 20 10.7k 9.6k 13.9k 13.3k 12.6k 15.6k 15k 14.3k 13k 10 22.2k 20.7k 28.8k 27.7k 26k 31.9k 31k 29.5k 27.3k table 24. r set vs. segment current and led forward voltage, v dd = 4.0v & 5.0v i seg (ma) v led v led 1.5v 2.0v 2.5v 3.0v 3.5v 1.5v 2.0v 2.5v 3.0v 3.5v 4.0v 40 v dd = 4.0v 8.6k 8.3k 7.9k 7.6k 5.2k v dd = 5.0v 11.35k 11.12k 10.84k 10.49k 10.2k 9.9k 30 11.6k 11.2k 10.8k 9.9k 7.8k 15.4k 15.1k 14.7k 14.4k 13.6k 13.1k 20 17.7k 17.3k 16.6k 15.6k 13.6k 23.6k 23.1k 22.6k 22k 21.1k 20.2k 10 36.89k 35.7k 34.5k 32.5k 29.1k 48.9k 47.8k 46.9k 45.4k 43.8k 42k ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 20 - 23 AS1117 datasheet - typical application 8x8 dot matrix mode the application example in figure 26 shows the AS1117 in the 8x8 led dot matrix mode. the led columns have common cathodes and are connected to the dig0:7 outputs. the rows are connected to the segment drivers. each of the 64 leds can be addressed separately. the columns are selected via the digits as listed in table 7 on page 12 . the decode enable register ( see page 13 ) must be set to ?00000000? as described in table 9 on page 14 . single leds in a column can be addressed as described in table 12 on page 15 , where bit d0 corresponds to segment g and bit d7 corresponds to segment dp. figure 26. application example as led dot matrix driver keyscan the key readback of the AS1117 can be used either for push buttons as well as switches. if only a single key is pressed (shorted) at a time no additional diodes are required. if a detection of multiple simultaneous keystrokes is required diodes within the keypath, as shown in figure 27 , are required. pressing multiple keys without the diodes would result in ambiguous results. figure 27. keyscan configuration supply bypassing and wiring in order to achieve optimal performance the AS1117 should be placed very close to the led display to minimize effects of electromagnetic interference and wiring inductance. furthermore, it is recommended to connect a 10f and a 0.1f ceramic capacitor between pins vdd and gnd to avoid power supply ripple ( see figure 16 on page 8 ). diode arrangement dig0 to dig7 seg a to g sep dp AS1117 sda scl irq v dd iset sda irq gnd scl 2.7v to 5v 9.53k p vdd resetn key sega segb segc segd seg e segf segg segdp irq diodes are optional and only required if multiple keystrokes must be detected simultaneously. if i2c self-adressing is used these two keys cannot be used for read- back and must be either hard wired opened or shorted. a short writes a logical ?1? whereas an open writes a logical ?0? as address bit. ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 21 - 23 AS1117 datasheet - package drawings and markings 10 package drawings and markings the AS1117 is available in the tqfn(4x4)-24 package. figure 28. tqfn(4x4)-24 package notes: unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 1. all dimensions are in millimeters; angles in degrees. 2. dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. dimension l1 represents terminal full back from package edge up to 0.1mm is acceptable. 3. coplanarity applies to the exposed heat slug as well as the terminal. 4. radius on terminal is optional. 24 19 20 21 22 23 789 10 11 12 4 5 6 2 3 1 13 14 15 16 17 18 m m symbol min typ max a 0.50 0.55 0.60 a1 0.00 0.05 a3 0.152ref b 0.18 0.23 0.28 d 4.00bsc e 4.00bsc d2 2.70 2.80 2.90 e2 2.70 2.80 2.90 symbol min typ max e 0.50bsc l 0.30 0.35 0.40 l1 0.00 0.10 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 22 - 23 AS1117 datasheet - ordering information 11 ordering information the devices are available as the standard products shown in table 25 . note: all products are rohs compliant. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is found at http://www.austriamicrosyst ems.com/technical-support for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.a ustriamicrosystems.com/distributor table 25. ordering information ordering code marking description delivery form package AS1117-bqft assu 64 led driver for mobile applications with error detection tape and reel tqfn(4x4)-24 ams ag technical content still valid
www.austriamicrosystems.com/led-driver-ics/AS1117 revision 1.00 23 - 23 AS1117 datasheet copyrights copyright ? 1997-201 0, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaet ten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used without the prio r written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specif ically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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